Abstract
High-energy ion implantation is coupled with the conventional planar technology to realize a silicon FET for power application. This device known as "Gridistor" is a multichannel FET with a p-type buried as gate. Boron implantation at various energies (600-900 keV) through a metallic mask are used to do a high-doped p-type gate layer, 0.8 µ thick and buried 1 µ below the surface. Since there is no implantation induced defects in the active regions of the device, low annealing temperature can be effectively used. As a consequence, the pattern sharpness is only limited by the definition of the mask. Using ion-etched gold layer as mask, 1 µ wide channels are made in a reproductible way. Few test structures have been made to check the behavior of implantation and planar technologies by measuring their capaci tances, transconductance, and I-V characteristics.
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