Ion-beam-induced charge-collection imaging of CMOS ICs

Abstract

Charge collection regions of the Sandia TA670 16-Kbit SRAM have been directly imaged using a technique we call ion-beam-induced charge-collection (IBICC) imaging. During the IBICC measurement, the integrated circuit is connected through its power ( V DD) or ground ( V SS) pins to a charge sensitive preamp whose output is pulse-height analyzed while the IC is exposed to a scanned 0.1-μm resolution microbeam of heavy ions. The IC, in effect, functions as its own detector of the magnitude of charge collected following a heavy-ion strike. In this work, we examine the effect on IBICC imaging of varying power supply bias over a range of 0 to 15 V. Comparison of the IBICC image with the design layout for this integrated circuit unambiguously identifies source and drain regions of n-channel transistors and drain regions of p-channel transistors in the memory array. We were not able to image p-channel source regions in either the V DD or V SS configuration. This result is clearly explained on the basis of the IC design. Comparison of IBICC images with previously measured single-event-upset (SEU) images of the TA670 provide a more complete understanding of the mechanisms that govern single-event upset in this SRAM. IBICC holds great promise as a diagnostic tool to quantify the underlying charge collection processes that are responsible for single event upset in complex integrated circuits. It can also be applied to device failure analysis in a manner similar to EBIC, with potentially higher resolution.