Abstract
This paper presents different strategies to improve the energy efficiency of nanoscaled Si based devices. Processing and device characteristics of nanowire (NW), Ge quantum dot (QD) metal oxide semiconductor field-effect transistors (MOSFETs) as well as tunnel FETs are discussed. A comparison of NW array devices containing uniaxially strained wires fabricated with SiO2/poly and HfO2/TiN gate stack is presented. The high uniaxial strain along the NWs reduces the band gap energy by approximately 140 meV and enhances the electron mobility. The hole mobility may be enhanced by proper choice of NWs orientation. Ideal inverse subthreshold slopes of n- and p-channel devices of 60 mV/dec at room temperature and Ion/Ioff ratios up to 1010 were obtained. Based on same 3D architecture Si and SiGe Tunnel FET are fabricated. For TFETs relatively high on-currents and good slopes <80 mV/dec were obtained. The typical ambipolar behavior of TFETs could be greatly suppressed by the use of a SiGe source tunneling junction.
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