Abstract
The bias-induced instability in hydrogenated amorphous silicon (a-Si:H), amorphous indium-gallium-zinc-oxide (a-IGZO) and low temperature poly-Si (LTPS) thin-film transistors (TFTs) is investigated. Gate bias-induced charge trapping at the active-layer/gate-insulator interface and into the gate-insulator, is the origin of positive threshold voltage (Vth) shift in a-Si:H and a-IGZO TFTs. The time dependence of the Vth shift (Vth) in a-Si:H and a-IGZO TFTs is explained by the charge trapping model rather than bond breaking model. The swing degradation-related Vth in LTPS TFTs, originates from the generation of grain boundary trap states, interface trap states and fixed oxide charge, when a negative gate-bias is applied. A good fit of the measured results is obtained by the bond-breaking model. Analysis of the charge trapping and bond breaking mechanisms is used to understand the electrical stability of the three kinds of TFTs.
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