(Invited) Single-Crystalline Silicon CMOS Fabrication on PET By Meniscus Force Mediated Layer Transfer Technique

Abstract

Fabrication of single-crystalline silicon CMOS circuits on a polyethylene terephthalate (PET) substrate has been carried out by meniscus force mediated layer transfer (MLT) at a very low temperature of 130°C. New cleaning process, self-limit etching, and high-energy ion implantation are the key for simultaneous transfer of both n- and p-channel islands to PET substrate. Transfer of SOI [p-type (100), 8–20 Wcm, 80-nm-thick] islands by MLT and CMOS fabrication process on a PET substrate are schematically summarized in Fig. 1. To form the “mid-air cavity”, SOI layer is patterned to dog-bone shaped channel islands (Fig. 1(a)). After ion implantation in the channel, source, and drain (S/D) regions and activation of impurities at 1000°C (Fig. 1(b)), 400-nm-thick buried oxide (BOX) layer underneath is etched by 25% hydrofluoric acid at 30°C to form thin SiO2 pillars that support the SOI layer above the mid-air cavity (Fig. 1(c)). Here, a pillar shaping implantation (PSI) was newly introduced to control the pillar shape. In addition, to precisely control the pillar size, self-limited etching technique was also introduced. Introduction of these two processes improved the layer transfer yield significantly, as mentioned later. Conformal thermal oxidation of the SOI layers is performed in dry oxygen at 1000 °C to form 11 nm SiO2 (Fig. 1(d)). The top oxide layer works as a barrier layer against contamination from the PET substrate, and the bottom oxide layer works as the gate insulator of the MOSFETs. The PET substrate is firstly aged at 130 °C for 10 min to suppress thermal expansion and shrinkage during the CMOS fabrication process, followed by scrub cleaning to remove precipitates. The SOI wafer and counter PET substrate are in close face-to-face contact with filling water, and they are heated on a hot plate at 80 °C for 10 min (Fig. 1(e)). When these substrates are separated, the SOI islands are transferred by the meniscus force generated between the SOI layer and the PET substrate (Fig. 1(f)). After the contact holes are opened, the gate and S/D electrodes are formed by aluminum evaporation and wet etching (Fig. 1(g)). The maximum process temperature after MLT is 130 °C at the post-bake for the lithography of contact holes and Al electrodes. By the introduction of above mentioned new processes, we have successfully fabricated CMOS on PET. The transfer yield was 99.86%. MOSFETs on PET show very high field effect mobilities (µFE) of 603 cm2V-1s-1 (n) and 172 cm2V-1s-1 (p) and low subthreshold swings (S factors) of 75.3 mV/dec (n) and 72.0 mV/dec (p), respectively. They show an on/off ratio of larger than 107 (at Vd = 0.1 V) with low off current (<10-13 A). CMOS inverters showed clear input/output characteristics under a supply voltage (Vdd) of 2.0 V, and we obtained clear output signal of 5-stage ring oscillator (RO). High-speed operation of 14.6 MHz was achieved on PET. The oscillation frequency of the transferred RO on PET is about 3.5 times as high as that of non-transferred RO on SOI wafer. This is because the parasitic capacitance in the case of RO on PET is significantly small. Figure 1