Abstract

While GaN high-electron-mobility transistors (HEMTs) provide the highest achievable RF power densities among all commercially available solid-state technologies, their rated output power densities are typically backed off substantially from the intrinsic limit of the device to ensure robust reliability. Power dissipation during RF operation is typically localized to an area near the drain-edge of the gate. The combination of this “hot spot” and the high electric fields that are present causes acceleration of known degradation mechanisms that limit device lifetime. In order to meet system reliability requirements, the rated output power is therefore constrained to keep the dissipated power, and thus the HEMT channel temperature, below a fixed limit. We previously showed that a high thermal conductivity nanocrystalline diamond (NCD) coating, 0.4 µm to 0.5 µm in thickness, on the top-side of the device nearest to the area of high power dissipation, can reduce channel temperature [1] while improving RF power performance [2] of AlGaN/GaN HEMTs compared to similar devices with SiNx passivation only. Here we continue this development with new designs that lead to further improvements in reduced junction temperature, RF output power, and operating frequency. The crucial design enhancements introduced here include a combination of thicker NCD coatings (>1 µm) and sub-micron gate lengths. Instead of a conventional AlGaN barrier, an InAlN barrier layer was used to reduce parasitic source/drain resistance, increase transconductance, and support gate lengths for millimeter wavelength operation (>30 GHz). In addition, the InAlN barrier is lattice-matched to GaN, which may provide reliability benefits by reducing the intrinsic strain in the layer compared to an AlGaN barrier. For devices with a 0.75 µm gate length and a 5 µm source-drain spacing, a maximum drain current of 1.8 A/mm, a peak fT of 29 GHz, and a peak fmax of 60 GHz was measured. Output power densities exceeded 5 W/mm and 3 W/mm with power-added efficiency of 52% and 42% for 4 GHz and 10 GHz operating frequencies, respectively. The effects of device design on electrical performance and the reduction in junction temperature will be discussed. Thermal simulations will be presented that verify the reduced channel temperature extracted through a calibrated pulsed I-V measurement technique [3] for NCD coated devices. [1] M.J. Tadjer et al., IEEE Electron Dev. Lett., vol. 33, no. 1, pp. 23-25 (2012). [2] D.J. Meyer et al., IEEE Electron Dev. Lett., vol. 35, no. 10, pp. 1013-1015 (2014). [3] J. Joh et al., IEEE T. Electron. Dev., vol. 56, no. 12, pp. 2895-2900 (2009).

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