(Invited) Processing and Integration Considerations for Successful Copper Electrodeposition in 3D IC Applications

Abstract

The impact of upstream integration and plating process conditions on the electrochemical filling of through-silicon vias (TSV) was investigated. For the same plating process, persistent bottom voiding was eliminated by tuning of the etch process. Thermal desorption mass spectrometry analysis showed the presence of chemical residues consistent with post-etch cleaning chemistry. The coverage of barrier and seed layers deposited by physical vapor deposition was investigated with TEM analysis, and found to be marginal in the vicinity of the bottom of high aspect ratio vias. From the plating side, the process was partitioned and tuned for bottom and top filling. Partial-fill studies were beneficial to identify the onset of bottom up fill for isolated and dense vias. By combining optimized upstream processing and plating process approaches with Generation 3 additive chemistry, bottom up fill was demonstrated for high aspect ratio features > 100 um deep. Finally, significant throughput improvement was shown by tuning the current-density-versus-time profile of the established baseline process.