(Invited) Porous Silicon for Energy Storage at Microscale: Supercapacitors

Abstract

The main driving force for continuing investigations on porous silicon (PS) is the expanding area for its potential application. Drug delivery, bio/chemical sensing, energy storage – those are just few samples of a wide range of applications of PS, mainly based on the extremely large surface area of the material.In this presentation we will discuss the application of porous silicon for energy storage at microscale, focusing on the electrochemical double layer capacitors (EDLC). EDLC, or so called supercapacitors, can store several orders of magnitude more energy than standard capacitors, and are slowly approaching the values typical for batteries. At the same time, supercapacitors offer much larger power densities than batteries do, also they can be charged very fast and can perform up to hundreds of thousands charge/discharge cycles. IoT and development of wearable and implantable devices would greatly benefit from this type of miniaturized energy storage element integrated on the same chip together with other active/passive elements and even with the energy harvester. Active carbon is still the most exploited material for supercapacitor electrodes, with carbon nanotubes and, especially, graphene with its large specific surface area, showing very promising results, at least at the laboratory scale. However, fabrication of carbon based electrodes usually includes a high temperature step which complicates their integration into the standard silicon microfabrication process. Porous silicon can be the solution here, as its processing is relatively simple and fully compatible with silicon microfabrication.Here we will review some recent and pioneering achievements in porous silicon based supercapacitor performance. The main obstacle for PS electrode application is chemical activity of the surface and low conductivity of electrode material. Several doping and passivation techniques will be discussed, such as metal sputtering, carbonization (graphene coating) and atomic layer deposition (ALD), all of which reasonably improve the performance (fig. 1). Applicability and efficiency of those techniques depend in large part on the pore size and thickness of the layer, which is also the main factor determining the capacitance of the device. A possible way towards the integration will be also shown by in-chip porous silicon supercapacitor design allowing increase the capacitance without expanding the foot print area of the device on a chip but just exploiting the bulk of silicon chip. A conformal coating with a precise thickness control is an important step in many fabrication processes, including also the supercapacitor. Currently, atomic layer deposition is the most suitable technique to fulfil the requirements. On the other hand, evaluation of the thickness and conformality of the coating inside the high aspect ratio pores is not so trivial task. A high resolution scanning electron microscopy (SEM) is not easy to perform in the case of small pores with such thin deposited layers. An interface contrast development for SEM can be used here, as will be discussed in this presentation. The technique is based on the excellent resistance of Al2O3 against SF6 plasma used for deep reactive ion etching of silicon. During the plasma etch step, the porous silicon “frame” is removed allowing to observe the released ALD layer or multilayer stack which was deposited inside the pores. Acknowledgement: This work has been partially funded by the Academy of Finland through the Finnish Center of Excellence in Atomic Layer Deposition. Figure 1