Abstract

The explosive growth of digital data poses increasing demand for novel hardware capable of storing, searching, and analyzing large amounts of data with high efficiency and low power consumption. In this context, resistive switching memories (RRAM) are under scrutiny for storage-class memories and in-memory computing to alleviate or even suppress the von Neumann bottleneck between memory and the central processing unit (CPU) [1]. RRAM devices provide an ideal solution to solve this dilemma, thanks to their high speed, low power, 3D integration and scalability. However, fundamental issues of switching variability and resistance stability must be understood and solved for a mature RRAM technology. This work addresses program and read variability in RRAM, presenting an overview of physical models to describe and predict statistical variations and their impact on device reliability.Variability issues can originate from cycle-to-cycle variations, cell-to-cell variations, and time-to-time variations. While cell-to-cell variations can be minimized by accurate control of the integration process, cycle-to-cycle and time-to-time variations are typically related to fundamental physical limitations, that need for a physical model and understanding for their solution. Cycle-to-cycle variations consist of switching variations, where the resistance of the low-resistance state (LRS) or high-resistance state (HRS) change from cycle to cycle due to random variations in the conductive path responsible for the state resistance. This is shown in Fig. 1, showing current-voltage characteristics of HfO2-RRAM devices with 1T1R architecture [2]. Devices show cycle-to-cycle variations for all switching parameters, including the set voltage Vset, the reset voltage Vreset, and the resistance of LRS and HRS. Variations decrease at increasing size of the conductive filament which is controlled by the compliance current IC, e.g., from IC = 8 μA (a) to 80 μA (b). These variations can be attributed to 2 fundamental sources of variations, namely shape variations, where the conductive-path shape changes from cycle to cycle at constant size, and number variations, where the size of the conductive path changes due to variations in the number of injected/migrated defects. Statistical physics-based models of the conductive path indicate that the normalized standard deviation of resistance sR/R increases with R for shape variations, and with R0.5 for number variations [3]. Fig. 2 shows the measured σR/R as a function of R, showing a transition from a slope 1 for LRS to a slope 0.5 for HRS in the log-log scale. This suggests that LRS variability is mainly due to shape variations, while HRS variability is due to number variation. The new variability model allows to understand and predict variations at variable set/reset conditions, such as variable voltage, current and time.While cycle-to-cycle program variations can be controlled by accurate program/verify techniques, read fluctuations can take place any time after program, thus cannot be easily suppressed. In particular, noise can lead to distribution broadening and device failure by unwanted mixing between HRS and LRS distributions [4]. A detailed analysis of current noise after the reset operation indicates 2 main contributions to fluctuation, namely random telegraph noise (RTN) and random walk (Fig. 3). The latter consists of sudden jumps of resistance, where the jump frequency decreases with time after programming. Random walk remains one of the main reliability issues of RRAM, since it contributes to the broadening of the resistance distributions after set/reset. Ways to mitigate or compensate the distribution broadening includes algorithms and material engineering. [1] H.-S. Philip Wong and S. Salahuddin, “Memory leads the way to better computing,” Nature Nanotechnology 10, 191 (2015).[2] S. Ambrogio, S. Balatti, A. Cubeta, A. Calderoni, N. Ramaswamy, and D. Ielmini, “Statistical fluctuations in HfOx resistive-switching memory (RRAM): Part I – Set/Reset variability,” IEEE Trans. Electron Devices 61, 2912 (2014).[3] D. Ielmini, “Resistive Switching Memories based on Metal Oxides: Mechanisms, Reliability and Scaling,” Semiconductor Science and Technology (2016).[4] S. Ambrogio, S. Balatti, V. McCaffrey, D. Wang, and D. Ielmini, “Noise-induced resistance broadening in resistive switching memory (RRAM) - Part II: Array statistics,” IEEE Trans. Electron Devices 62, 3812 (2015). Figure 1

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