(Invited) Performance Enhancement Technologies in III-V/Ge MOSFETs

Abstract

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/ integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for enhancing the MOSFET performance with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. By using these HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated with high electron (690 cm2/Vs) and hole (550 cm2/Vs) mobility. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm By utilizing this channel engineering, 55 nm-Lch quantum well channel InAs-OI n-MOSFETs have been demonstrated with superior short channel effect immunity and fairly high on current.