Abstract
Ion Beam Etching (IBE) is emerging as the technology of choice for patterning of advanced embedded MRAM devices (<40nm CD, <1:1 aspect ratio) for 28nm logic integrated circuits. Experimental and simulated etch data, for a representative STT-RAM structure with 38 to 45 nm CD and 150 to 200 nm pitch, show a reduction in the sidewall re-deposition when operating at high angle and high ion energy. Ion energies above 1000eV provide best profile performance in the main etch. However, this leads to intermixing of stack materials and device shorts. Ion energies below 100eV are used in an overetch step to remove the intermixed layer. Excellent beam divergence and energy spread over the entire ion energy range are paramount and requires co-optimization of of the ion beam source and grid. To avoid damage of patterned MgO by air exposure, IBE and encapsulation PECVD must be integrated on one vacuum platform. Sub 1ppm short fail patterning results have been obtained with optimized IBE and encapsulation processes.
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