(Invited) Nano-Precision Deep Reactive Ion Etching of Monocrystalline 4H-SiCOI for Bulk Acoustic Wave Resonators with Ultra-Low Dissipation

Abstract

Introduction Micromechanical resonators with ultra-low energy dissipation are essential for a wide range of applications, including chemical sensors, and inertial sensors for navigation in GPS-occluded environments [1]. While ease of batch fabrication along with high-fidelity wafer-level processing have made monocrystalline silicon (Si) the preeminent substrate for seamlessly integrated microelectromechanical systems (MEMS), Si may not be suited to address the ever-growing demand for high-precision MEMS instruments robust to harsh environments. As the quest for low dissipation is plateauing with the direct observation of Si’s quantum limit, monocrystalline Silicon Carbide (SiC) is under active investigation for its promise of room-temperature mechanical Qs exceeding 100M at 6 MHz, owing to its extraordinary Akhiezer damping, which sits 30x below that of Si. Such high Qs are critical to demonstrate navigation-grade resonant gyroscopes with Angle Random Walk (ARW) near 0.00017°√hr, matching the performance of ring laser gyroscopes while being potentially vastly more portable and affordable. Ultra-low Dissipation SiC Resonators This paper reports on the implementation of capacitive SiC resonators with micron-scale transduction gaps, exhibiting fQ=1.25x1014 Hz, a 5-fold improvement over Si’s limits which has already been reported in [3]. These results are particularly interesting because SiC is more susceptible to thermoelastic damping (TED) than Si, by a factor near 5x. To break through the barrier set by material properties that grant an inferior Q TED limit, we have fabricated clamped-clamped beam [4], bulk acoustic wave (BAW) disk [5-6], and Lamé mode resonators [3] using high-density plasma etching of monocrystalline 4H-SiC-on-Insulator (SiCOI) fusion-bonded substrates in STS AOE. We have experimentally verified that these resonators have a decreasing susceptibility to TED in accordance with COMSOL simulations. While the volume-preserving Lamé mode is virtually TED-free in a tether-less square configuration, the unavoidable introduction of tethers and sidewall roughness due to the finite precision of deep reactive ion etching (DRIE) of SiC exacerbates TED. Method While the overarching fabrication details have been published elsewhere [3-6], the SiC DRIE optimization in STS AOE is presented here for the fist time. Plasma etching of SiC can be accompanied by the undesired formation of micropillars because the metallofluorinated NiCxFy compound accumulates on the sidewall and flakes off under various conditions. This issue is circumvented by tailoring the DRIE recipe to reduce the growth rate of the passivation layer. With that in mind, we typically flow an excess of Ar compared to SF6 to starve the trenches from F-based species that tend to polymerize with exposed C atoms. We optimize the coil and platen power to generate a self-bias DC voltage of nearly 280V and reduce the pressure to 8mTorr to prevent any sidewall damage due to the lack of passivation on the sidewall. Results and Conclusions Fig. 1 reveals that selecting bulk acoustic wave (BAW) mode resonators and operating deep in their adiabatic regime enables to the barrier set by TED in monocrystalline SiC, unlike for flexural resonator that operate near the Debye peak. However, surface TED can still limit Q if asperities form on the sidewall of the SiC BAW resonators; we prevent their formation by tailoring the DRIE recipe to limit the deposition of the NiCxFy passivation and by intermittently removing the passivation in wet etchants (Fig. 2). Moreover, removing the passivation enables to etch high-aspect-ratio trenches in SiCOI wafers with nanoscale smoothness (Fig. 3). By designing acoustically deaf SiC Lamé resonators [3], we reveal that SiCOI substrates can support ultra-low dissipation resonators, which fQ=1.25x10 14 Hz, 5x improvement over the limit of monocrystalline Si (Fig. 4). Through the development of nano-scale precision SiC DRIE, this paper opens the door to a myriad of high-performance chip-scale SiC instruments that can be deployed in harsh environments.