(Invited) Modeling Extended Defects in Semiconductor Devices

Abstract

We perform analysis of several key aspects of the extended defect formation and their impact on silicon and GaN transistors. Heterogeneous epitaxy has been an enabling technique in transistor design since 90 nm technology node. The most widely used stress engineering technique is based on introducing crystal lattice mismatch stress by growing SiGe on Si. Depending on Ge content and on the size and shape of the selectively grown SiGe islands, the lattice mismatch stress can be high enough to introduce edge dislocations and stacking faults. Once the dislocations are created, they can move, driven by stress gradients towards more energetically favorable locations. An example of creating geometrical features to attract dislocations towards certain area has been demonstrated experimentally for epitaxial SiGe layers exceeding critical thickness on non-planar Si surfaces [1]. We reproduce such behavior by numerical minimization of elastic strain energy of an ensemble of {111} stacking faults (Fig. 1). Whenever dislocations manage to escape such herding and encroach into sensitive transistor areas, we perform quantum transport analysis to estimate the impact of a dislocation on electron scattering, on-state and off-state currents for Si nanowires with 5nm design rules. Another area where extended defect monitoring is essential is the GaN power switches. To achieve low buffer leakage in AlGaN/GaN HEMT for high voltage applications, it has been proposed to intentionally dope the GaN buffer with carbon [2]. This creates acceptor traps in the buffer to pin the Fermi Level at ~0.86 eV above the valence band [3]. A p-type buffer is thus formed and isolated from the Two-Dimensional Electron Gas (2DEG), which aggravates current collapse [3][4]. However, experimental results show that the magnitude of current collapse is less than suggested by modeling which can be attributed to the buffer being connected to the 2DEG through threading dislocations [3]. In this work, we perform 3D TCAD analysis of the impact of threading dislocations on the buffer trapping/de-trapping and current collapse. [1] R. Gatti, F. Boioli, M. Grydlik, M. Brehm, H. Groiss et al., Appl. Phys. Lett., 98, 121908 (2011) [2] E. Bahat-Treidel, F. Brunner, O. Hilt et al., IEEE Trans. Electron Devices, 57(11), 3050–3058 (2010) [3] M. J. Uren, M. Silvestri, M. Cäsar, G. A. M. Hurkx, J. A. Croon, J. Šonský, and M. Kuball, IEEE Electron Device Lett. 35(3), 327–329 (2014) [4] M. J. Uren, J. Möreke, and M. Kuball, IEEE Trans. Electron Devices 59 (12), 3327–3333 (2012) Fig. 1. Dislocations in epitaxial SiGe layer move towards the bottom of a V-shaped trench in Si wafer (a). Each additional dislocation reduces the total elastic strain energy of the structure (b). Figure 1