Abstract
In this work we present process developments for the integration of graphene into a 200mm silicon technology platform. We investigated different process module developments like graphene synthesis on silicon compatible materials like germanium and a non-destructive deposition of dielectric materials on the 2D graphene sheet. Moreover, the combinations of these processes for various concepts of contacting on a full 8” wafer are considered. Finally, we discuss certain metrology methods of a standard Si-CMOS technology and their adaption for an accurate process control of the graphene related processes. We evaluate all processes with respect to their silicon baseline technology compatibility and discuss challenges for future developments towards the developments of large-scale integration of graphene into a silicon technology.
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