(Invited) Issues on Interfacial Oxide Layer (IL) in EOT Scaling of High-k/Metal Gate CMOS for 22nm Technology Node and Beyond

Abstract

According to the International Technology Roadmap for Semiconductors (ITRS), scaling to the 22 nm technology generation and beyond is facing significant challenges related to the timely implementation of high-k/metal gate stacks, including appropriate tuning of the metal gate work function, adequate channel mobility, and reliability. Scaling equivalent oxide thickness (EOT) becomes more challenging as it will reflect interfacial oxide layer (IL) scaling causing some issues such as mobility degradation and difficulty in achieving PMOSFET Vt target. This paper discusses issues on IL in the scaling the EOT of high-k/metal gates tacks.