(Invited) Isotopically Engineered Silicon Testbeds for Advanced CMOS and Quantum Information

Abstract

Silicon isotope engineering invokes a new paradigm into materials science for development of advanced CMOS technology and practical quantum computers [1]. Current development of planer-type CMOS devices confronts an immediate issue for downscaling limit, demanding a basal changeover to gate-all-around transistors employing three-dimensional (3D) nanostructures, such as vertical nanowires or stacked nanosheets. Recently, nanoscale metrology of 3D electronic devices is enabled by means of atom probe tomography (APT) having nearly atomic resolution [2]. We extended this APT technique to verify Si self-diffusion in isotopically modulated nanopillars, which allowed spatial visualization of individual isotope atoms crossing the heterointerface [3]. As a result, Si self-diffusivity in gate-oxidized nanopillars having a diameter of ~200 nm was found to remain the same as the one measured for standard planar oxidation. More recently, process tracking technique based on transmission electron microscope (TEM) was established for identical Si nanopillars, which led to unveil a gate-oxidation overview for various conditions [4]. In addition, the silicon isotope engineering provides a crucial solution to eliminate unwanted decoherence for Si-based spin qubits. We adopted the isotope engineering to tailor high-quality CVD-grown 28Si epi-wafers [1], where state-of-the-art Si-MOS nanoelectronic devices were implemented to demonstrate two-qubits operations encoded by single donor electron and nuclear spins [5]. In parallel, the isotopically enriched wafers were employed to demonstrate single and two spin-qubit operations in 28Si-MOS quantum dots (QDs) that were defined by standard CMOS lithography [6]. Meanwhile, we accomplished isotope enrichment of strained-Si/SiGe quantum-well (QW) heterostructures, where the QDs were placed away from gate-oxide interface traps. Thanks to efficient suppression of magnetic nuclear-spin noise, the isotopically enriched 28Si/SiGe QDs prolonged electron-spin dephasing time, consequently recording the highest single-spin gate fidelities of 99.93% in benchmark test [7]. However, it was revealed that inherent charge noise induces temporal fluctuation of qubit frequency. Moreover, the low-energy excited states responsible for Si valley degeneracy should be well-lifted for the higher-fidelity operations, including spin-qubit readout and initialization. Our recent 28Si/SiGe heterostructures exhibit large valley splitting, demonstrating a well-defined QW interface having fewer atomic-scale steps [8]. And also, major impurities of carbon and oxygen can be suppressed below 1016 cm-3. In order to address the remaining source of step generation, we developed direct imaging scheme for crystallographic tilting effects on the basis of the TEM diffraction [9]. It has been identified that the local lattice rotation is preferentially caused in the proximity of the dislocations having threading components. This fact provides experimental signature for the global step generation at the QW interface.This work has been supported by MEXT Quantum Leap Flagship Program (MEXT Q-LEAP) Grant Number JPMXS0118069228, JST-ACCEL Grant Number JPMJAC1301, and the Center for Spintronics Research Network, Keio University. The authors acknowledge fruitful collaborations with Yasuyoshi Nagai, Yasuo Shimizu, Tetsuo Endoh, Seigo Tarucha, Mark Eriksson, Andrew Dzurak and Andrea Morello.[1] K. M. Itoh and H. Watanabe, MRS Communications 4, 143 (2014).[2] D. J. Larson et al., MRS Bulletin 41, 30 (2016).[3] R. Kiga et al., J. Appl. Phys. 127, 045704 (2020).[4] T. Wako et al., in preparation.[5] J.T. Mohonen et al., Nature Nanotechnol. 9, 986 (2014).[6] M. Veldhorst et al., Nature Nanotechnol. 9, 981 (2014); M. Veldhorst et al., Nature 526, 410 (2015).[7] J. Yoneda et al., Nature Nanotechnol. 13, 102 (2018).[8] S. Miyamoto et al., IEEE IEDM – Technical Digest, pp.6.4.1 - 6.4.4 (2018).[9] K. Takeuchi et al., in preparation.