(Invited) Impact of Some Processing Steps onto the Strain Distributions in FD-SOI CMOS Planar Devices: A Contribution of Dark-Field Electron Holography

Abstract

Clever strategies have been set up and are today routinely used to generate strains of desired directions and amplitudes in the channels of CMOS transistors. Unfortunately, many of the processing steps which follow this strain engineering have a strong impact on the final strain state of these channels, sometimes even not foreseen. Here, we report on the use of Dark-Field Electron Holography to image strain in the channels of FD-SOI CMOS devices all along their fabrication route, from the fabrication of the co-integrated Si-SiGe layers to contact formation. We show that, in general, good background knowledge of the different materials characteristics and of the physics of the process, as well notions of structural mechanics, are enough to understand then eventually model the impact of these processing steps. However, our results evidence a particular mechanical weakness of the SiGe/BOX interface following the Ge condensation process which seriously challenges strain manipulation in the pMOS channel.