(Invited) High-Speed Plasma Etching of SiC Wafer Toward Backside Thinning

Abstract

Semiconductor power devices are necessary to convert electric voltage, current, and frequency for efficient electrical energy use. Although most of them are now fabricated using silicon (Si) semiconductors, wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), which have a larger bandgap than Si, are attracting attention for efficient conversion improvement. Continuous research and development of crystal growth, crystal evaluation, and device improvement technologies over many years have led to the commercialization of SiC transistors and inverters. One of the issues of SiC power devices is their comparatively higher cost than Si power devices; therefore, reducing the cost is essential for their wide application. Not only high quality and low-cost crystal growth technology is essential for SiC power devices but also a low-cost processing technique. Most power transistors have a vertical structure. Device wafer substrate thickness must be thin to minimize onstate resistance; however, there is a limiting thickness necessary for handling a wafer during device processing. Therefore, wafer thickness must be reduced from a backside after devices are fabricated on it. Although a mechanical process such as grinding is suitable for the backside thinning of silicon, it is costly for SiC because of extended processing time due to its hardness and the high wear rate of an expensive diamond grinding wheel. Additionally, the process leaves subsurface damage on a processed surface, decreasing device chip strength and reliability.We investigated the applications of plasma chemical vaporization machining (PCVM), a plasma etching method using high-pressure plasma, to the SiC backside thinning process. In conventional plasma etching for device fabrication, reactive ion etching (RIE) is employed to ensure anisotropy, an important requirement for pattern transferability. In the RIE process, applied pressure cannot be increased because the mean-free path of the gas molecules must be long enough for ion acceleration. Owing to the limited amount of gas molecules contributing to the reaction, the processing rate is limited to approximately 1 μm/min. PCVM is a chemical etching process in which neutral radicals are employed as the active species. Although it lacks anisotropy, an etching rate that is difficult to achieve with RIE can be attained by increasing working pressure. We developed a wafer-sized electrode, i.e., an electrode with the same surface geometry as a wafer, with many gas supply holes fabricated for wafer-level thinning. It was found that the SF6 plasma generated over the entire wafer surface by reducing the working pressure from atmospheric pressure to a few tenths of the atmospheric pressure without helium dilution. The results of the experiments showed that the thickness of the entire 2-inch 4H-SiC (0001) wafer could be reduced at a high removal rate of 15 μm/min by increasing rf power. The removal rate mainly depended on power density and was relatively insensitive to the processing parameters such as processing gap and gas flow rate. In addition, it was discovered that almost the same removal rate could be achieved with rf power being proportional to the area of the wafer even if the wafer diameter was increased. It was demonstrated that the thickness of the commercially available two-inch wafer could be thinned to approximately 100 μm by 20-min plasma etching. Furthermore, a commercially available SiC MOSFET chip was used for a backside thinning experiment to evaluate the influence of plasma irradiation on the MOS interface using the C–V characteristic measurements. Although the deterioration of the SiO2/SiC interfacial properties due to ultraviolet (UV) irradiation was reported, there was no change in the C–V characteristic before and after exposure to SF6 plasma. The constant C–V characteristic might be because the amount of UV light reaching from the backside to frontside surface is small owing to the thin penetration depth.PCVM for the backside thinning of a SiC wafer contributes to cost reduction owing to reduction in processing time and the nonuse of an expensive diamond grinding wheel. It also improves the reliability of fabricated devices because it leaves no subsurface damage on the backside of a wafer, resulting in the wide-spread utilization of low-power consumption SiC power devices for a sustainable society.