(Invited) High-Speed and Low-Power Electronics – from Vertical III-V Nanowires to Oxides

Abstract

The future of electronics is facing ever more stringent requirements in terms of low power consumption and versatile functionality, which the industry workhorse Si CMOS will not be able to fulfil on its own [1]. III-V vertical nanowire (vNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs), integrated on Si substrates, are promising complements to Si CMOS for high-speed and low-power applications. A major challenge for III-V vNW MOSFETs is the minimisation of parasitic capacitances and the realisation of a high-quality gate oxide [2]. In this talk, first, a comprehensive and consistent summary of the quality of Al2O3/HfO2 gate oxides in III-V vNW FETs will be presented. Besides their application in transistors, oxides have attracted a lot of interest due to their possible use as memristors for non-volatile memory as well as for in-memory and neuromorphic computing [3]. In the second part of this talk, ongoing work will be presented on new approaches to tune oxide properties for memory functionality.The appeal of III-V vNW FETs lies in the high mobility/injection velocity of III-V materials, the possibility for complex band structure design, and the decoupling of the gate length from the device footprint [4]. In high-electron-mobility transistors (HEMTs), the superior III-V materials qualities have been translated to operation frequencies of f T ≈ 700 GHz [5] and f max ≈ 1.5 THz [6], which is up to three times as high as in Si. However, HEMTs face limitations in terms of electrostatic scaling, so that MOSFETs are attracting increased interest for high-frequency applications. In III-V vNW MOSFETs, which can be scaled more aggressively than HEMTs, f T and f max of about 150 GHz has been demonstrated, which is limited by parasitic capacitances related to the gate oxide [7]. Another oxide-related challenge, common to different architectures of III-V MOSFETs, is the stability of the threshold voltage V T due to defects in the gate oxide; the same oxide defects can also cause low-frequency noise, hysteresis in the current-voltage characteristics, and losses in the high-frequency gains. The same effects are observed in III-V vNW TFETs with inverse subthreshold slopes below 60 mV/decade and here, results will be presented for all of these effects.Besides the characterisation of gate oxide defects, approaches to non-volatile thin-film oxide resistive memory will be presented, which are based on the engineering of strain to achieve ferroelectricity, or of ionic conductivity to control resistance via a Schottky barrier [8]. Recently, it was demonstrated that oxide memory can be integrated directly on top of III-V vNW transistors [9] so that together, oxides and vNW transistors offer extensive design space to complement Si CMOS for highly specialised high-speed and low-power applications.[1] S. Salahuddin et al., Nature Electronics 2018, doi: 10.1038/s41928-018-0117-x[2] J. Franco et al., IEEE IEDM 2017, doi: 10.1109/IEDM.2017.8268347[3] An Chen, Solid-State Electronics 2016, doi: 10.1016/j.sse.2016.07.006[4] H. Riel et al., MRS Bulletin 2014, doi: 10.1557/mrs.2014.137[5] E.-Y. Chang et al., Applied Physics Express, doi: 10.7567/apex.6.034001[6] X. Mei, IEEE EDL 2015, doi: 10.1109/LED.2015.2407193[7] O.-P. Kilpi et al., Electronics Letters, doi: 10.1049/el.2020.0266[8] S. Cho et al., Nature Communications 2016, doi: 10.1038/ncomms12373[9] M.S. Ram et al., IEEE EDL 2020, doi: 10.1109/LED.2020.3013674