Abstract
Ge-on-insulator (GeOI) MOSFET structures are advantageous to suppress off-state current levels while keeping the high-performance originated from the high electron and hole mobility. On the other hand, the low thermal budget of the fabrication processes could provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs. In this paper, electrical properties and processes of strained Ge nanowire pMOSFETs and strained GeOI nMOSFETs for high performance applications are presented. Ultra-high hole mobility of over 1900 cm2/Vs and 4-times enhancement of the nMOSFET drive current are demonstrated for the p- and nMOSFETs, respectively. Poly-Ge trigate p- and nFETs on buried oxide (SiO2) layers are also presented for 3D-LSIs. Reasonable operation of sub-100 nm devices and improvement of the current drivability are demonstrated.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.