(Invited) Electrical Performance Improvement in 300mm Ge-Based Devices

Abstract

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation. Reference Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009).Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013).H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014).S. Goley, M. K. Hudait, Materials, 2301 (2014).Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)