(Invited, Digital Presentation) 50 Ns Ultrafast Memory Operation in 2D Heterostructured Non-Volatile Memory Device

Abstract

2D heterostructures have been extensively investigated as next-generation non-volatile memory (NVM) devices. In the last decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate voltage (V FG) trajectory measurements [1,2]. Systematic comparisons of MoTe2, WSe2, and MoS2 channel devices revealed that the tunneling behavior between the channel and FG is controlled by three kinds of current-limiting paths, i.e., tunneling barrier, 2D/metal contact, and pn junction in the channel. Based on the understanding of the memory operation mechanism through the V FG trajectory measurement, we propose the best all 2D NVM device structure with a direct tunneling path between source/drain electrodes and floating gate for ultrafast memory operation. Indeed, a 50 ns program/erase operation is successfully achieved [3]. Moreover, we examined the dielectric breakdown strength (E BD) of h-BN under short voltage pulses for the origin for this ultrafast operation, because a high dielectric breakdown strength allows a large tunneling current. Surprisingly, an E BD = 26.1 MV/cm for h-BN is realized under short voltage pulses, largely exceeding the E BD = ~12 MV/cm from the DC measurement. This suggests that the high E BD of h-BN can be the physical origin of the ultrafast operations. In this talk, I would like to discuss the future perspective of 2D NVM application.[1] T. Sasaki, KN, et al., "Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage", Small, 2020, 16, 2004907.[2] T. Sasaki, KN, et al., "Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage Trajectory", ACS nano, 2021, 15, 6658.[3] T. Sasaki, KN, et al., "Ultrafast Operation of All 2D-Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength of h-BN", Adv. Funct. Mater. (under revision).