(Invited) Cobalt Interconnects at 36nm Beol Pitch and Beyond: Material Challenges & Circuit-Level Performance Impact

Abstract

Cobalt metallization in the back-end-of-line (BEOL) presents several interesting opportunities and challenges1-5. In this work, we evaluate the performance of Co interconnects at narrow BEOL pitch using chemical vapor deposition (CVD) for Co and a Ta-based barrier layer. In-line electrical measurements demonstrate a higher RC-delay for Co interconnects relative to Cu interconnects. Various challenges associated with Co metallization at narrow-pitch are identified. Simulations based on temperature-coefficient of resistivity (TCR) measurements are used to identify various cross-over points in which Co line resistance becomes lower than Cu line resistance depending on width, aspect ratio and barrier material/thickness. In addition to in-line characterization of damascene Co interconnects, we employ a state-of-the-art multi-scale modeling approach to evaluate overall BEOL-loaded device performance for both Co and Cu conductors. We consider a single-driver reference circuit6,7 to evaluate the delay penalty for Co v. Cu metallization at several representative pitches. Ab initio simulations are employed to determine lower-limits of Co via resistance and surface scattering for a variety of possible barrier materials and thicknesses. These results are fed into a field solver to calculate stage delay for several representative logic gates, including a 3-input NAND and a 2-input multiplexer (MUX). Results indicate that despite having a higher line resistance, a net improvement in stage delay can be achieved for a suitably-tuned Co via resistance. Critical dimension (CD) sensitivity is also characterized for both Co and Cu metallization schemes. These results highlight some of the challenges and potential advantages of using Co-based conductors in advanced interconnects beyond the 7nm technology node. This work was performed by the Research and Development Alliance Teams at various IBM Research and Development Facilities. Figure 1