(Invited) Challenges in Ultra-Small Device Manufacture

Abstract

As semiconductor devices become smaller and approach the limits of conventional photolithography, achieving high quality pattern transfer becomes ever more challenging and expensive. Non-conventional lithographies may realize feature size below 10 nm but the etch challenges are not addressed. Here we examine how block copolymer lithography can be used to address both scaling and pattern transfer. In block copolymer (BCP) lithography, BCPs on a surface can self-assemble into regular arrangements for creation of ordered arrays on holes and line spacing. Recently we have extended these techniques to selectively include hard mask type materials into the polymer pattern. These then form an inorganic pattern of the same polymer structure and allow high contrast pattern transfer to a variety of substrates. Typical examples from the work are shown in Figure 1. We illustrate this work by hard masks based on NO, W and Zn and demonstrate device functionality using electrical characterization.However, no matter how advanced this form of lithography becomes, grand challenges remain in scaling. The biggest of these is layer-to-layer registry or overlay of features. In this work, we extend our methodology to develop a form of selective area deposition. Selective deposition, if successful, could remove a number a key lithographic steps and lower fabrication costs. We use a methodology that combines etch techniques to enhance surface chemical contrast and so facilitate selective deposition. Recent results that allow direct deposition of dielectric deposition are provided. Figure 1