(Invited) Bipolar Switching of Phase Change Memory for Enhanced High-Temperature Stability

Abstract

Phase change memory (PCM) devices are among the most mature technology for storage class memory and embedded memory for, e.g., the internet of things (IoT). One of the key limitation of PCM is the crystallization of the amorphous phase taking place at relatively low temperature, e.g., 150°C for Ge2Sb2Te5(GST) [1]. The low crystallization point prevents the use of PCM in high-temperature applications, such as automotive and embedded chips requiring retention up to 260°C. To overcome the temperature limitations, phase change materials with higher stability against crystallization have been presented, such as C-doped GST [2] and Ge-rich GST [3]. However, increasing the crystallization point raises stability issues for the set (crystalline) state due to the time evolution of the grain boundary structure [4]. Therefore, other techniques to improve the high-temperature reliability of PCM, e.g., by algorithm and/or alternative storage concepts, must be developed.This work addresses the bipolar switching of PCM. Mushroom-type devices with confined bottom electrode (or heater), where subjected to bipolar operation: the application of a positive voltage to a PCM in the amorphous phase leads to threshold switching and set transition to low resistance, while the application of a negative voltage causes a reset transition to high resistance, similar to the one typically observed in resistive switching memory (RRAM). The reset voltage is lower than the melting temperature, thus evidencing that reset transition is not due to a phase change, such as melting and amorphization. Bipolar switching is interpreted by ionic migration of elemental species, such as Ge, Sb and Te in GST. The initial positive voltage causes crystallization with approximately uniform distribution of atomic elements, then the applied negative voltage causes ionic migration driven by the electric field and accelerated by the local Joule heating. In particular, cation-type Ge and Sb migrate toward the top electrode, thus leaving a depleted region in correspondence of the bottom electrode. The high concentration of vacancies and possibly microvoids in the depleted region are responsible for the high resistance which can reach the few GΩ range. Application of a positive voltage results in ionic redistribution and the decrease of resistance. The stability of the bipolar reset state was addressed at both room temperature and high temperature. The bipolar reset state does not show any resistance drift, confirming that the storage concept does not rely on the transition to the amorphous phase. Similarly, there is no evidence for crystallization at high-temperature for the bipolar reset state. While the conventional reset state, obtained under either positive or negative voltage, shows crystallization around 150°C, the bipolar reset show a gradual decline of resistance suggestive of redistribution (e.g., diffusion) of atomic species in the depleted gap. A residual resistance window of 10x is achieved at 250°C, supporting the use of bipolar switching PCM for high temperature application. For instance, bipolar switching PCM might be suitable to sustain retention tests for few minutes at 260°C, which are required for embedded applications [5]. These results might thus open novel application spaces by overcoming the limitations of phase transition in conventional PCM. [1] T. Kato and K. Tanaka, “Electronic properties of amorphous and crystalline Ge2Sb2Te5 films,” Jpn. J. Appl. Phys. 44, 7340 (2005).[2] G. Navarro, et al., “Trade-off Between SET and Data Retention Performance Thanks to Innovative Materials for Phase-Change Memory,” IEDM Tech. Dig. 570 (2013). [3] H. Y. Cheng, et al., “A High Performance Phase Change Memory with Fast Switching Speed and High Temperature Retention by Engineering the GexSbyTez phase Change Material,” IEDM Tech. Dig. 51 (2011). [4] N. Ciocchini, E. Palumbo, M. Borghi, P. Zuliani, R. Annunziata, D. Ielmini, “Modeling resistance instabilities of set and reset states in phase change memory with Ge-rich GeSbTe,” IEEE Trans. Electron Devices 61, 2136 (2014). [5] P. Zuliani, et al., “Overcoming Temperature Limitations in Phase Change Memories With Optimized GexSbyTez,” IEEE Trans. Electron Devices 60, 4020 (2013).