Abstract

As the semiconductor industry is approaching the 5nm node technology, conventional patterning schemes cannot meet the ever-increasing requirements for alignment imposed by device miniaturization. Area-Selective Deposition (ASD) can potentially alleviate such manufacturing challenges by enabling bottom-up material deposition. The most used and successful approach to achieve ASD envisage a combination of Atomic Layer Deposition (ALD) and surface passivation, such as, self-assembled monolayer (SAM).Among the potential applications, dielectric on dielectric (DoD) ASD emerged as one of the most important for multilayer nano interconnects (e.g.: enabling fully self-aligned vias). In this context, along with the difficulties encountered in preserving a confined material growth, the challenges extend to the fact that the deposited dielectric must exhibit well-defined properties, such as low-dielectric constant. Indeed, the integration an interconnect dielectric deposition process in an ASD scheme is arduous. Vapor-phase deposition of SiO2-like materials typically requires high process temperature as well as strong oxidants or O2-plasma. These are not compatible with the organic passivation films exploited to create well-distinguished local surface chemistries, which is essential to enable selective-material deposition.In this talk, 1-octadecanethiol (ODT) well-known selective chemisorption on Cu over SiO2 is exploited to achieve AS-DoD deposition and understand the surface-driven mechanism that enables a selective material growth. In addition, the proposed ASD scheme in combination with nanoscale adhesion force characterization is used to tackle a critical lack in ASD metrology: monitoring the passivation film directly on patterned substrate. Finally, the challenges and results obtained as an ODT-compatible dielectric deposition process for interconnect applications are discussed in this talk.ASD enabled by metal passivation for Hf3N4, Hf-Silicate, Al2O3, and Al-silicate ALD are explored and presented on Cu/SiO2 patterned substrates, with critical dimension as low as 10nm.

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