Investigation on the effect of multiple parameters towards thermal management in 3D Stacked ICs

Abstract

Three dimensional (3D) integration technology, involving the vertical stacking of multiple chips using through-silicon vias (TSVs), has emerged as a promising solution to improve the performance of microelectronic devices. However, the complex structures and the consequent increase in power density exacerbate the challenge of thermal management in the device including multiple chips. In order to ensure the reliability of 3D stacked chips during operation, it is important to have a better understanding of the thermal distribution of a 3D chip stack. In this paper, a detailed analysis of 3D IC packaging from thermal reliability perspective is presented, performed by finite element simulations. The effect of the variation of structure-related parameters on steady-state temperature profiles in the stack has been analyzed, including TSVs diameter and pitch, the thickness of SiO 2 , as well as the thermal conductivity of under fill. The research provides useful insights for thermal management of 3D IC packaging.