Investigation of Timing Jitter in NAND and NOR Gates Induced by Power-Supply Noise

Abstract

This paper analyses power-supply noise induced timing variations in NAND and NOR logical blocks. The focus of this work is on the NAND and NOR blocks used in nonover-lapping clock generation circuits used for switched capacitor sigma-delta analog-to-digital converters. Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using parameters from two manufacturing processes, 0.35 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m and 0.18 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m, are presented. The power-supply noise is assumed to have a gaussian amplitude distribution with independent power and ground noise. The results show that the timing jitter dependency on power-supply noise has a low-pass frequency characteristic and is approximately linear as we have previously shown for the inverter case. Furthermore, the jitter impact decreases as transistors move deeper into the submicron domain and for comparable transistor sizings, NAND blocks have a lower timing sensitivity to PSN compared with NOR blocks.