Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

Abstract

The trigger voltage walk-in effect has been investigated by designing two different laterally diffused metal—oxide—semiconductor (LDMOS) transistors with an embedded silicon controlled rectifier (SCR). By inserting a P+ implant region along the outer and the inner boundary of the N+ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5 μm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse (TLP) and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.