Investigation of the Off-State Degradation in Advanced FinFET Technology—Part I: Experiments and Analysis

Abstract

Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed to describe corresponding mechanisms. However, very limited data on OFF-state degradation is available, especially in FinFET technology. In the first part of this article, OFF-sate degradations of 7-nm FinFET technology are reported for the first time. The physics mechanisms in OFF-state degradation are proposed by combining TCAD simulations and comprehensive experimental characterizations. It is found that an enhanced secondary carriers effect is responsible for the OFF-state degradation with contributions from both trapped electrons and holes. Furthermore, typical locations of electron traps and hole traps under the OFF-state degradation are identified. The abnormal leakage degradation is explained in a consistent manner. The analysis here leads to a compact reliability model reported in part II.