Investigation of the Effect of Parasitic Inductances on the Current Balancing of Parallel-Connected Discrete SiC JFETs

Abstract

SiC JFETs demonstrate quite a few unique properties like low specific on-resistance, high temperature operation potential benefiting from the simple physical structure, and normally-on characteristics, making it quite attractive for applications like solid-state circuit breakers. However, the parallel operation of the SiC JFETs is not as well documented as that of SiC MOSFETs or Si IGBTs. This paper investigates the parallel operation of the SiC JFETs and the effects of drain, source parasitic inductances of the discrete SiC JFET on the current sharing during parallel operation. The impact of parasitic inductances on current sharing for the parallel connected SiC JFETs are experimentally validated and analyzed. Further, methods to mitigate such unbalanced current sharing is proposed.