Investigation of strain relaxation in patterned strained silicon-on-insulator structures by Raman spectroscopy and computer simulation

Abstract

It is well established that the strain in sSOI wafers can be maintained during the high temperature processing steps required by CMOS technology if suitable precautions are taken during patterning of the sSOI wafer into device islands [1]. Routinely a rigid capping layer, such as SiO 2 is used to reduce strain relaxation caused by cutting the strained film into small islands. Here, we study the simplest but scientifically relevant case, where in the absence of capping layers or any other precautions, strain relaxation by film patterning and high temperature annealing can be observed. The thermal stability of bi-axial strain is maintained solely by a non-epitaxial bonded interface with the amorphous buried oxide in sSOI after patterning and subsequent high temperature annealing.