Abstract

The etching properties of C6F6/Ar/O2 in both an inductively coupled plasma (ICP) system and a capacitively coupled plasma (CCP) system were evaluated to investigate the effects of high C/F ratio of perfluorocarbon (PFC) gas on the etch characteristics of SiO2. When the SiO2 masked with ACL was etched with C6F6, for the CCP system, even though the etch selectivity was very high (20 ~ infinite), due to the heavy-ion bombardment possibly caused by the less dissociated high-mass ions from C6F6, tapered SiO2 etch profiles were observed. In the case of the ICP system, due to the higher dissociation of C6F6 and O2 compared to the CCP system, the etching of SiO2 required a much lower ratio of O2/C6F6 (~1.0) while showing a higher maximum SiO2 etch rate (~400 nm/min) and a lower etch selectivity (~6.5) compared with the CCP system. For the ICP etching, even though the etch selectivity was much lower than that by the CCP etching, due to less heavy-mass-ion bombardment in addition to an adequate fluorocarbon layer formation on the substrate caused by heavily dissociated species, highly anisotropic SiO2 etch profiles could be obtained at the optimized condition of the O2/C6F6 ratio (~1.0).

Highlights

  • As the semiconductor device size has decreased to nanoscale due to the high integration of the circuit, the critical dimension has decreased to a few nanometers and the device structure has changed from 2D to 3D

  • In this study, using a perfluorocarbon (PFC) gas having a high C/F ratio of C6F6 and low global warming potential (GWP) of 7, the differences in the plasma characteristics and the etch characteristics were compared between an inductively coupled plasma (ICP) system and a capacitively coupled plasma (CCP) system

  • The possibility of using an ICP system instead of a conventional CCP system in high aspect ratio contact (HARC) SiO2 etching masked with amorphous carbon layer (ACL) was investigated for C6F6/Ar/O2 gas mixtures

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Summary

Introduction

As the semiconductor device size has decreased to nanoscale due to the high integration of the circuit, the critical dimension has decreased to a few nanometers and the device structure has changed from 2D to 3D.

Results
Conclusion
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