Investigation of Single-Bit and Multiple-Bit Upsets in Oxide RRAM-Based 1T1R and Crossbar Memory Arrays

Abstract

In this paper, the susceptibility of oxide-based resistive switching random memory (RRAM) to heavy ion strikes is investigated. A physics-based SPICE model calibrated with ${\hbox{HfO}}_{\rm x}$ RRAM is employed for circuit and array-level simulations. The RRAM state-flipping is attributed to the transient photocurrents at neighboring transistors. Single-bit-upset (SBU) caused by either single-event upset (SEU) or multiple-event upset (MEU) is modeled and simulated in the one-transistor and one-resistor (1T1R) array, which corroborates with experimental observations. In addition, circuit simulation is performed to investigate the impact of transient-induced soft errors in a $1024 \times 1024$ crossbar array. The sensitive locations in crossbar arrays are the driver circuits at the edge of the array. The simulations show that the crossbar array with ${\hbox{HfO}}_{\rm x}$ RRAM is of high radiation tolerance thanks to the V/2 bias scheme. However, multiple-bit upset (MBU) may occur if using other oxide materials with lower operation voltage. Voltage spikes generated at the edge of the array may propagate along rows or columns as there is no isolation between cells in the crossbar array.