Investigation of Process-Induced Warpage of 3D-Stacked Memory Packaging

Abstract

Due to the advantages of low cost and high integration, 3D-stacked packaging is widely used in the industry for encapsulation of muli-chip memories. However, warpage is inevitable during the packaging process due to the mismatch of coefficient of thermal expansion (CTE) between the chips, adhesive, substrate and Epoxy Molding Compound (EMC). Different packaging structures will lead to different warpage values, so predicting and optimizing the warpage of multiple memory devices is still a challenging task. In many studies, EMC materials are often simplified as elastic materials or elastic materials only dependent on temperature, but EMC is actually viscoelastic materials.In this paper, according to the industry company requirements, two stack structures for memory chips, step type, and staggered type, are considered for the study. The viscoelastic parameters of EMC were determined by Dynamic Mechanical Analysis (DMA). The relaxation modulus was described in the form of the Prony series using the generalized maxwell model. Then, the finite element model for the 3D-stacked packages is set up and simulations are carried out. The main parameters such as the thickness of the memory chip, the thickness of the adhesive, and the thickness of EMC were selected to conduct orthogonal experiments and range analysis to study the effects of different packaging structures and various factors on warpage. The results show that the packaging structure of the chip has an effect on chip warpage, and the influence degree is EMC thickness > adhesive thickness > chip thickness. Proper arrangement of stacked chips can reduce the warpage.