Investigation of Performance Degradation in 600-V HD-GITs Under Power Cycling Tests

Abstract

Hybrid drain-embedded gate injection transistors (HD-GITs) are one of the most promising technologies for normally-OFF operation. However, the relevant reliability research is relatively lacking. In this article, comprehensive results of degradation performance in 600-V HD-GITs are presented. First, the thermomechanical stress is applied to the device under test (DUT) through an accelerated power cycling test (PCT) setup. Then, thermal and electrical parameters shift under the PCTs are monitored periodically by the PCT setup and the curve tracer. As can be seen from the measurement results, as the PCT progresses, the device not only exhibits package-level degradation, but chip-level degradation also occurs gradually. Notably, leakage current that increases with degradation appears to be a potential choice for lifetime modeling. Finally, the state-of-the-art failure analysis (FA) techniques, such as emission microscopy (EMMI), scanning electron microscope (SEM), focused ion beam (FIB) cutting, and others, are performed. The results of FAs validated the monitoring data, and the root cause of the degradation of the thermal resistance and electrical parameters was eventually confirmed as the solder degradation and the structural damage of the source and gate. Such an investigation can serve as a valuable reference for the reliability of GaN power devices.