Investigation of memory effect with voltage or current charging pulse bias in MIS structures based on codoped Si-NCs

Abstract

Co-doped Si-NCs have been introduced into MIS structures with HfO x gate dielectric layers. The fabricated test structures were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Presented results are promising for applications of Si-NCs in memory structures.