Abstract
Laser spike anneal (LSA) is applied in advanced CMOS device fabrication to achieve efficient dopant activation without excess dopant diffusion. Dwell time, defined as the ratio of full width at half maximum of laser beam and beam scan speed, is found to be a critical and effective knob in LSA processes. In this work, different dwell time of LSA and its impact on dope activation, junction profile, and compatibility with embedded SiGe (e-SiGe) was studied. Dwell time in the range of 800us to 275us has been investigated. LSA processes with different dwell time result in similar dopant activation and almost identical doping profile. On the other hand, reduced dwell time resulted in significant improvement in wafer warpage and overlay performance, when LSA is applied on CMOS devices with e-SiGe S/D pMOSFET. With electrical results consistent with offline characterization, this work indicated that lower dwell time LSA is more flexible and compatible with e-SiGe process for advanced CMOS devices.
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