Investigation of Key Technologies for Poly-Si/TaN/HfLaON/IL ${\rm SiO}_{2}$ Gate-Stacks in Advanced Device Applications

Abstract

We demonstrated for the first time integration of a poly-Si/TaN/HfLaON/IL SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stacks into high-performance sub-30-nm nMOSFETs using a gate-first process flow successfully. The properties of TaN/HfLaON/IL SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stacks were studied. The results showed that the HfLaON gate dielectric material exhibited excellent thermal stability and electrical characteristics. A three-step dry etching method used to etch poly-Si/TaN/HfLaON/IL SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stack was proposed to provide an effective pathway for patterning the complex gate-stacks. At V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> =0.9 V, the drive current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of 410 μA/μm was achieved at an OFF-state leakage current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of 180 nA/μm. The threshold voltage of saturation extracted at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> of 3 μA/μm was 0.14 V. The subthreshold slope of 92 mV/decade and drain induced barrier lowering of 93 mV/V were obtained.