Investigation of ferroelectric field-effect transistors using a replacement metal gate process

Abstract

The negative-capacitance field-effect transistor (NCFET) is an emerging steep switching device that utilizes the negative capacitance of the ferroelectric layer to induce voltage amplification in the gate stack. In this study, an NCFET was fabricated by using a replacement metal gate process, which can avoid the influence of high temperature processes on ferroelectric film. The different sub-threshold slope (SS) characteristics of forward gate voltage sweep and reverse gate voltage sweep were investigated. The results show that the different SS characteristics may originate from asymmetrical polarization–voltage (P–V) hysteresis loops of metal–ferroelectric–insulator–silicon capacitance in the NCFET. Moreover, the influences of Hf/Zr ratio, annealing temperature and capacitance size on ferroelectric characteristics were investigated. The experimental results show that there is an optimal Hf/Zr ratio and annealing temperature that maximizes the residual polarization (P r). For ferroelectric field-effect transistor (FeFET) memory design, the largest P r should be chosen to increase retention time. For ferroelectric NCFET logic design, the negative capacitance can be adjusted by changing the Hf/Zr ratio and annealing temperature to achieve better capacitance matching between positive capacitance and negative capacitance. It is expected that experimental results may provide some guidance for the design and performance enhancement of FeFETs and NCFETs.