Investigation of ESLR effects in the OCVD measurement used for minority carrier lifetime determination in high power silicon diodes

Abstract

The effect of surface leakage on the OCVD (open-circuit voltage decay) measurement used to determine carrier lifetime in the ν-region of high power silicon p+-ν-n+ diodes had been discussed (Bassett 1969 BASSETT , R. J. , 1969 , Solid-St. Electron. , 12 , 385 .[Crossref] , [Google Scholar]). Several possible techniques for eliminating the effect of an ESLR (effective surface leakage resistance) on the low-level OCVD across p+-ν-n+ and n+-ν-p+ silicon diodes have been investigated. A model in which on internal voltage drives a leakage current through the ESLR during the OCVD is proposed. When highly conductive contacts to the p+ and n+-regions are employed, carriers can be extracted across the whole of the area of the p-n junction and the low-high junctions of the diodes. A hydrofluoric/nitric acid treatment was found to be satisfactory in most of the diodes investigated to erradicate any ESLR effect on the low-level OCVD. However, it was concluded that a number of almost identical diodes (e.g. at least six) must be tested before any confidence could be placed in the results. The technique may not be suitable for small area diodes (e.g. < 0.1 cm2) or power diodes with largo lifetimes (e.g. > 1 ms). A technique for elimination of ESLR effects in a single largo area p+-ν-n+ silicon diode is described.