Abstract
The three-pulse CV measurement technique has been used to study electron and hole charge trapping and de-trapping in SiO2/LaLuO3 gate stacks on p-type silicon substrate. Variation of flat-band voltage shift due to electron and hole trapping with charging time and pulse amplitude has been investigated. The pulsed CV measurements have been taken at various ramp rates and times to delineate the influence of interface states. The time constant of interface states responses estimated experimentally. The three-pulse CV measurements at different ramp rates are also used to evaluate the reliability of the measurement technique.
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