Investigation of Electrochemical Oxidation Behaviors and Mechanism of Single-Crystal Silicon (100) Wafer under Potentiostatic Mode

Weijia Guo,Kui Liu,Hui Deng,Senthil Kumar Anantharajan

doi:10.3390/coatings10060586

Abstract

Electrochemical oxidation (ECO) has been used widely to oxidize single crystal Si wafers. Aiming at optimizing the ECO assisted machining methods, the oxidation behaviors of single- crystal silicon (100) wafer under potentiostatic mode are experimentally investigated. It is shown that the Si wafer can be electrochemically oxidized and the oxidized film thickness reaches to 239.6 nanometers in 20 min. The hardness of the oxidized surface is reduced by more than 50 percent of the original surface. The results indicate that the oxide thickness and the hardness can be controlled by changing the voltage. Based on the experimental findings, a hypothesis on the ECO mechanism under potentiostatic mode was proposed to explain the fluctuations of current density under specific applied voltage. The occurrence of the multiple peaks in the current density curve during the oxidation process is due to the formation of discharge channels, which was initiated from the defects at the interface between the oxide bottom and the substrate. This breaks the electrical isolation and leads to the discontinuous growth of the electrochemical oxide layer. The present work contributes to the fundamental understanding of the ECO behaviors for the single-crystal Si (100) wafer under potentiostatic mode.

Highlights

Chemical mechanical polishing (CMP) is one of the most commonly used polishing method for silicon wafers and it is a crucial step in the processing of silicon wafers in semiconductor manufacturing technology [1]
The experimental results clearly indicate that the applied voltage has significant influence on the oxidation rate and the oxidation behavior
Due to the breakdown of the insulating oxide, which initiated from the defects at the interface between the oxide bottom and the substrate, discharge channels would form simultaneously during the electrochemical oxidation (ECO) progression process

Summary

Introduction

Chemical mechanical polishing (CMP) is one of the most commonly used polishing method for silicon wafers and it is a crucial step in the processing of silicon wafers in semiconductor manufacturing technology [1]. CMP is a combination of both chemical and mechanical processes. New types of defects will be introduced from the CMP process and these defects are critical for some sub-micro meter features, which makes the development of additional processes required. Another problem of CMP is that both the equipment and consumables are expensive. Because of the high hardness and strong chemical inertness, the material removal rate (MRR) of silicon wafer by CMP has reached its limit [4]. All the above-mentioned drawbacks and Coatings 2020, 10, 586; doi:10.3390/coatings10060586 www.mdpi.com/journal/coatings

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