Investigation of dual-phase-lag heat conduction model in a nanoscale metal-oxide-semiconductor field-effect transistor

Abstract

This paper investigates the numerical simulation of non-Fourier transient heat transfer in a two-dimensional sub-100nm metal-oxide-semiconductor field-effect transistor (MOSFET). The dual-phase-lag (DPL) model with a specific normalization procedure is introduced for the modeling of nanoscale heat transport. The boundary conditions are selected similar to what existed in a real MOSFET device, both uniform and non-uniform heat generations within the transistor are applied, and the end parts of the top boundary which are in contact with the metallic material are left open. A temperature-jump boundary condition is used on all boundaries in order to consider the boundary phonon scattering at micro and nanoscale. A three-level finite difference scheme has been employed to generate the numerical results which are illustrated for a silicon sub-100nm MOSFET corresponding to the Knudsen number of 10. The results are presented at real times less than 50ps to avoid the three-dimensional effects. It is concluded that the combination of the DPL model with mixed-type temperature boundary condition is able to predict the heat flux and temperature distribution obtained from the Boltzmann transport equation (BTE) more accurate than the ballistic-diffusive equations (BDE). After verification of our results, the thermal field and the hotspot temperature within the bulk silicon are presented and the effect of adding a layer of silicon-dioxide to the transistor on its thermal behavior has been investigated.