Investigation of compact hardware implementation of the advanced encryption standard

Abstract

A compact and efficient implementation of the advanced encryption standard (AES) is the desirable encryption IP core for any practical low-end embedded application. In this paper, we investigate various architectures for compact AES implementations in 0.18-mum CMOS technology. We first investigate a new compact digital hardware implementation of AES s-boxes applying the discovery of linear redundancy in AES s-boxes. Although the new circuit has a small size, the speed of this implementation is also reduced. Encryption architectures without key scheduling employing four s-boxes and only one s-box are implemented using our new AES s-boxes, as well as based on other compact s-box structures. The comparison of six implementations indicates that the implementation using four s-boxes based on arithmetic operations in GF(24) has the best trade-off of area and speed. Therefore, using this s-box implementation, a complete encryption-decryption architecture with key scheduling employing the four s-box structure is implemented. In order to be adaptive to various practical applications, we optimize the implementation with the four s-box structure to support five different operation modes