Investigation into the thermal effects of thinning stacked dies in three-dimensional integrated circuits

Abstract

In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradient, including spikes in individual device temperatures. In a non-thinned circuit the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally. In this paper we experimentally examine the thermal resistance from an active heater to the heatsink in a two-tier bump-bonded 3D stacked system. A simplified structure is introduced to enable such measurements without the time and cost associated with the full fabrication of such a system. Die thinning is seen to have a pronounced effect on the thermal response. Thinning the top tier from 725 μm to 20 μm results in a nearly 7 times increase in the thermal resistance from heater to heatsink.