Investigation, Evaluation, and Optimization of Stray Inductance in Laminated Busbar

Abstract

Wiring inductance has a critical effect on electrical, thermal, and electromagnetic compatibility (EMC) performances in inverters. Therefore, the low stray inductance laminated busbar, as a state-of-the-art pathway interface, is widely used in high-power inverters. However, the asymmetrical stray inductances of the laminated busbar may cause different voltage and thermal stresses for semiconductor devices of the same power stage. In order to achieve low and symmetrical stray inductances in the laminated busbar, this paper presents the investigation, evaluation, and optimization of the stray inductances of the laminated busbar. Based on the current commutation loop (CCL) analysis, the investigation of two-layer, three-layer, and multilayer laminated busbars is proposed through three-dimensional (3-D) finite element analysis (FEA) simulations. It can be found that the skin effect, mutual effect, CCL length, CCL separation distance, and split plate significantly influence the stray inductance of laminated busbars. Furthermore, the multilayer laminated busbar structure for multilevel neutral point clamped (NPC) inverter is derived. On the basis of the theoretical analysis, CCL stray inductances of a three-layer laminated busbar are extracted by means of FEA simulation and an improved impedance resonant measurement in a single-phase H-bridge high-power inverter. Insulated gate bipolar transistor (IGBT) voltage overshoot waveforms further validate the stray inductance asymmetry of the laminated busbar. A compromise between the stray inductance and symmetry is proposed in the three-layer laminated busbar. Finally, several feasible guidelines for the optimization of the laminated busbar design are introduced.