Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs

Abstract

We systematically compared the 5 ​nm-node triple-gate FinFET and the vertically-stacked GAA NWFET (gate-all-around nanowire FET) from the electrical and thermal perspectives, and found the degraded current drivability and the severe SHEs (self-heating effects) are the major concerns of the GAA NWFET. Then, we intentionally studied the impact of nanowire (NW) design parameters, including the NW doping concentration ranging from 1015 ​cm−3 to 5 ​× ​1018 ​cm−3, NW height ranging from 4 ​nm to 8 ​nm and NW width ranging from 4 ​nm to 8 ​nm, on the performance of the GAA NWFET. Each NW configuration has been evaluated through the on-state current (Ion), intrinsic gate delay (τ), thermal resistance (Rth) and max lattice temperature difference (△TL,Max). We found reducing NW doping concentration, increasing NW height or increasing NW width to the specific value can improve the current drivability. With respect to the SHEs immunity, increasing NW width is more effective compared with varying the other two NW design parameters.