Abstract
Gate-open failures in power semiconductors occur when the gate-bond wire cracks or lifts-off leading to loss of gate control. In molded discrete devices, this failure mode may occur intermittently making it very challenging to analyze and detect. In this paper, intermittent gate-open failures are comprehensively investigated in the context of discrete SiC MOSFETs. First, the MOSFETs behavior under various possible gate-open failure scenarios is analyzed in detail through simulations. Several SiC MOSFETs are aged on a DC power cycling setup and gate-open failure mechanism is verified through systematic multi-step failure analysis which includes on-board characterization, non-destructive C-SAM analysis, decapsulation and optical inspection followed by SEM analysis of the failed devices. To understand the potential mechanism behind gateopen failure in SiC MOSFETs, thermo-mechanical FEA analysis is performed on a high-fidelity model which shows interfacial shear stress at gate-bond. Further, a robust on-board technique for reliable cycle-by-cycle detection of gate-open faults is proposed. The proposed technique is experimentally verified for all possible fault scenarios and shown to detect faults in as low as 150ns. It is shown that compared to traditional DESAT protection scheme, the proposed mechanism can prevent potential shoot-through events that may be caused by gate-open failure.
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