Abstract
This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of RF CMOS technology. Compared with a standard multi-finger device with uniform gate-finger spacing, a device with non-uniform gate-finger spacing represents an improvement of 8.5% for the drain—source breakdown voltage (BVds) and of 20% for the thermally-related drain conductance. A novel compact model is proposed to accurately predict the variation of BVds with the total area of devices, which is dependent on the different finger spacing sizes. The model is verified and validated by the excellent match between the measured and simulated avalanche breakdown characteristics for a set of uniform and non-uniform gate-finger spacing arranged nMOSFETs.
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